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xicor, inc. 1994, 1995, 1996 patents pending 7032 -1.1 6/17/97 t1/c0/d0 sh 1 characteristics subject to change without notice 64k 32k 16k x25648/49, x25328/29, x25168/69 8k x 8 bit 4k x 8 bit 2k x 8 bit v cc supervisory circuit w/serial e 2 prom features low vcc detection and reset assertion reset signal valid to vcc=1v save critical data with block lock tm protection block lock tm protect 0, 1/4, 1/2 or all of serial e 2 prom memory array in circuit programmable rom mode long battery life with low power consumption ?1 m a max standby current <5ma max active current during write <400 m a max active current during read 1.8v to 3.6v, 2.7v to 5.5v and 4.5v to 5.5v power supply operation 2mhz clock rate minimize programming time 32 byte page write mode self-timed write cycle 5ms write cycle time (typical) spi modes (0,0 & 1,1) built-in inadvertent write protection power-up/power-down protection circuitry write enable latch write protect pin high reliability available packages 14-lead soic (x2564x) 14-lead tssop (x2532x, x2516x) 8-lead soic (x2532x, x2516x) description these devices combines two popular functions, supply voltage supervision and serial e 2 prom memory in one package. this combination lowers system cost, reduces board space requirements, and increases reliability. the users system is protected from low voltage condi- tions by the devices low vcc detection circuitry. when vcc falls below the minimum vcc trip point, the system is reset. reset /reset is asserted until vcc returns to proper operating levels and stabilizes. the memory portion of the device is a cmos serial e 2 prom array with xicors block lock tm protection. the array is internally organized as x 8. the device features a serial peripheral interface (spi) and software protocol allowing operation on a simple four-wire bus. the device utilizes xicors proprietary direct write tm cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years. block diagram data register command decode & control logic reset control low voltage sense programming, block lock & icp rom control x - decode logic status register page decode logic serial e 2 prom array high voltage control si so sck cs reset /reset v cc wp 7036 frm 01 32 8
x25648/49, x25328/29, x25168/69 2 pin descriptions serial output (so) so is a push/pull ser ial data output pin. dur ing a read cycle , data is shifted out on this pin. data is cloc k ed out b y the f alling edge of the ser ial cloc k. serial input (si) si is a ser ial data input pin. all opcodes , b yte addresses , and data to be wr itten to the memor y are input on this pin. data is latched b y the r ising edge of the ser ial cloc k. serial clock (sck) the ser ial cloc k controls the ser ial b us timing f or data input and output. opcodes , addresses , or data present on the si pin are latched on the r ising edge of the cloc k input, while data on the so pin change after the f alling edge of the cloc k input. chip select ( cs ) when cs is high, the de vice is deselected and the so output pin is at high impedance and unless a non v olatile wr ite cycle is underw a y , the de vice will be in the standb y po w er mode . cs lo w enab les the de vice , placing it in the activ e po w er mode . it should be noted that after po w er-up , a high to lo w tr ansition on cs is required pr ior to the star t of an y oper ation. write protect ( wp ) when wp is lo w and the non v olatile bit wpen is ?? non v olatile wr ites to the de vice status register are disab led, b ut the par t otherwise functions nor mally . when wp is held high, all functions , including non v olatile wr ites to the status register oper ate nor mally . if an inter nal status register wr ite cycle has already been initiated, wp going lo w while wpen is a ? will ha v e no eff ect on this wr ite . subsequent wr ite attempts to the status register under these conditions will be disab led. the wp pin function is b loc k ed when the wpen bit in the status register is ?? this allo ws the user to install the de vice in a system with wp pin g rounded and still be ab le to prog r am the status register . the wp pin functions will be enab led when the wpen bit is set to a ?? reset ( reset /reset) reset /reset is an activ e lo w/high, open dr ain out- put which goes activ e whene v er vcc f alls belo w the mini- m um vcc sense le v el. it will remain activ e until vcc r ises abo v e the minim um vcc sense le v el f or 200ms . pin configuration pin names 7036 frm t01 symbol description cs chip select input so serial output si serial input sck serial clock input wp program protect input v ss ground v cc supply voltage reset /reset reset output 14-lead soic x25648/49 nc cs cs so wp v ss 1 2 3 4 5 6 7 reset /reset sck si nc 14 13 12 11 10 9 8 nc v cc v cc nc 7036 frm 02 8-lead soic x25328/29 cs wp so 1 2 3 4 reset /reset 8 7 6 5 v cc 14-lead tssop x25328/29 so wp v ss 1 2 3 4 5 6 7 reset /reset sck si 14 13 12 11 10 9 8 nc v cc nc x25168/69 v ss sck si cs nc nc nc nc x25168/69
x25648/49, x25328/29, x25168/69 3 principles of operation the de vice is designed to interf ace directly with the syn- chronous ser ial p er ipher al interf ace (spi) of man y popu- lar microcontroller f amilies . the de vice monitors v cc and asser ts reset /reset output if the supply v oltage f alls belo w a preset minim um v tr ip . the de vice contains an 8-bit instr uction register . it is accessed via the si input, with data being cloc k ed in on the r ising edge of sck. cs m ust be lo w dur ing the entire oper ation. all instr uctions ( t ab le 1), addresses and data are tr ans- f erred msb rst. data input on the si line is latched on the rst r ising edge of sck after cs goes lo w . data is out- put on the so line b y the f alling edge of sck. sck is static , allo wing the user to stop the cloc k and then star t it again to resume oper ations where left off . write enable latch the de vice contains a wr ite enab le latch. this latch m ust be set bef ore a wr ite oper ation is initiated. the wren instr uction will set the latch and the wrdi instr uction will reset the latch (figure 3). this latch is automatically reset upon a po w er-up condition and after the completion of a v alid wr ite cycle . status register the rdsr instr uction pro vides access to the status reg- ister . the status register ma y be read at an y time , e v en dur ing a wr ite cycle . the status register is f or matted as f ollo ws: the wr ite-in-prog ress (wip) bit is a v olatile , read only bit and indicates whether the de vice is b usy with an inter nal non v olatile wr ite oper ation. the wip bit is read using the rdsr instr uction. when set to a ?? a non v olatile wr ite oper ation is in prog ress . when set to a ?? no wr ite is in prog ress . the wr ite enab le latch (wel) bit indicates the status of the wr ite enab le latch. when wel=1, the latch is set high and when wel=0 the latch is reset lo w . the wel bit is a v olatile , read only bit. it can be set b y the wren instr uction and can be reset b y the wrds instr uction. the bloc k loc k bits , bl0 and bl1, set the le v el of bloc k loc k tm protection. these non v olatile bits are pro- g r ammed using the wrsr instr uction and allo w the user to protect one quar ter , one half , all or none of the e 2 pr om arr a y . an y por tion of the arr a y that is bloc k loc k protected can be read b ut not wr itten. it will remain pro- tected until the bl bits are altered to disab le bloc k loc k protection of that por tion of memor y . 7036 frm t03 bits 4 and 5 of the status register will be read as ? s and m ust be wr itten as ? s on all status register wr ites . 7 6 5 4 3 2 1 0 wpen flb 1 1 bl1 bl0 wel wip 7036 frm t02 status register bits array addresses protected bl1 bl0 x2564x x2532x x2516x 0 0 none none none 0 1 $1800?1fff $0c00?0fff $0600?07ff 1 0 $1000?1fff $0800?0fff $0400?07ff 1 1 $0000?1fff $0000?0fff $0000?07ff table 1. instruction set *instr uctions are sho wn msb in leftmost position. instr uctions are tr ansf erred msb rst. 7036 frm t04 instruction name instruction format* operation wren 0000 0110 set the write enable latch (enable write operations) sflb 0000 0000 set flag bit wrdi/rflb 0000 0100 reset the write enable latch/reset flag bit rsdr 0000 0101 read status register wrsr 0000 0001 write status register (blocklock,wpen & flag bits) read 0000 0011 read data from memory array beginning at selected address write 0000 0010 write data to memory array beginning at selected address
x25648/49, x25328/29, x25168/69 4 the read only fla g bit sho ws the status of a v olatile latch that can be set and reset b y the system using the sflb and rflb instr uctions . the flag bit is automatically reset upon po w er up . the non v olatile wpen bit is prog r ammed using the wrsr instr uction. this bit w or ks in conjunction with the wp pin to pro vide prog r ammab le hardw are wr ite protec- tion (t ab le 2). when wp is lo w and the wpen bit is pro- g r ammed high, all status register wr ite oper ations are disab led. in circuit programmable rom mode this mechanism protects the bloc k loc k and w atchdog bits from inadv er tant corr uption. it ma y be used to per- f or m an in circuit prog r ammab le r om function b y hard- wir ing the wp pin to g round, wr iting and bloc k loc king the desired por tion of the arr a y to be r om, and then pro- g r amming the wpen bit high. read sequence when reading from the e 2 pr om memor y arr a y , cs is rst pulled lo w to select the de vice . the 8-bit read instr uction is tr ansmitted to the de vice , f ollo w ed b y the 16- bit address . after the read opcode and address are sent, the data stored in the memor y at the selected address is shifted out on the so line . the data stored in memor y at the ne xt address can be read sequentially b y contin uing to pro vide cloc k pulses . the address is auto- matically incremented to the ne xt higher address after each b yte of data is shifted out. when the highest address is reached, the address counter rolls o v er to address $0000 allo wing the read cycle to be contin ued inde nitely . the read oper ation is ter minated b y taking cs high. ref er to the read e 2 pr om arr a y sequence (figure 1). t o read the status register , the cs line is rst pulled lo w to select the de vice f ollo w ed b y the 8-bit rdsr instr uc- tion. after the rdsr opcode is sent, the contents of the status register are shifted out on the so line . ref er to the read status register sequence (figure 2). write sequence pr ior to an y attempt to wr ite data into the de vice , the ?r ite enab le latch (wel) m ust rst be set b y issuing the wren instr uction (figure 3). cs is rst tak en lo w , then the wren instr uction is cloc k ed into the de vice . after all eight bits of the instr uction are tr ansmitted, cs m ust then be tak en high. if the user contin ues the wr ite oper ation without taking cs high after issuing the wren instr uction, the wr ite oper ation will be ignored. t o wr ite data to the e 2 pr om memor y arr a y , the user then issues the write instr uction f ollo w ed b y the 16 bit address and then the data to be wr itten. an y un used bits are speci ed to be ? s? the write oper ation minimally tak es 32 cloc ks . cs m ust go lo w and remain lo w f or the dur ation of the oper ation. if the address counter reaches the end of a page and the cloc k contin ues , the counter will roll bac k to the rst address of the page and o v erwr ite an y data that ma y ha v e been pre viously wr itten. f or the p age wr ite oper ation (b yte or page wr ite) to be completed, cs can only be brought high after bit 0 of the last data b yte to be wr itten is cloc k ed in. if it is brought high at an y other time , the wr ite oper ation will not be completed (figure 4). t o wr ite to the status register , the wrsr instr uction is f ollo w ed b y the data to be wr itten (figure 5). data bits 0 and 1 m ust be ?? data bits 4 and 5 m ust be ?? table 2. 7036 frm t06 status register status register device pin block block status register wel wpen wp# protected block unprotected block wpen, bl0, bl1 bits 0 x x protected protected protected 1 1 0 protected writable protected 1 0 x protected writable writable 1 x 1 protected writable writable
x25648/49, x25328/29, x25168/69 5 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 7 6 5 4 3 2 1 0 d a t a out cs sck si so msb high imped ance instr uction 16 bit address 15 14 13 3 2 1 0 7036 frm 03 while the wr ite is in prog ress f ollo wing a status register or e 2 pr om sequence , the status register ma y be read to chec k the wip bit. dur ing this time the wip bit will be high. reset /reset operation the reset (x25xx3) output is designed to go lo w whene v er v cc has dropped belo w the minim um tr ip point, v tr ip . the reset (x25xx5) output is designed to go high whene v er v cc has dropped belo w the minim um tr ip point, v tr ip . the reset /reset output is an open dr ain output and requires a pull up resistor . operational notes the de vice po w ers-up in the f ollo wing state: the de vice is in the lo w po w er standb y state . a high to lo w tr ansition on cs is required to enter an activ e state and receiv e an instr uction. so pin is high impedance . the wr ite enab le latch is reset. the flag bit is reset. reset signal is activ e f or t purst . data protection the f ollo wing circuitr y has been included to pre v ent inad- v er tent wr ites: a wren instr uction m ust be issued to set the wr ite enab le latch. cs m ust come high at the proper cloc k count in order to star t a non v olatile wr ite cycle . figure 1. read e 2 prom array sequence
x25648/49, x25328/29, x25168/69 6 figure 2. read status register sequence figure 3. write enable latch sequence 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 7 6 5 4 3 2 1 0 d a t a out cs sck si so msb high imped ance instr uction 7036 frm 04 0 1 2 3 4 5 6 7 cs si sck high imped ance so 7036 frm 05
x25648/49, x25328/29, x25168/69 7 figure 4. write sequence figure 5. status register write sequence 32 33 34 35 36 37 38 39 sck si cs 0 1 2 3 4 5 6 7 8 9 10 sck si instruction 16 bit address d a t a byte 1 7 6 5 4 3 2 1 0 cs 40 41 42 43 44 45 46 47 d a t a byte 2 7 6 5 4 3 2 1 0 d a t a byte 3 7 6 5 4 3 2 1 0 d a t a byte n 15 14 13 3 2 1 0 20 21 22 23 24 25 26 27 28 29 30 31 6 5 4 3 2 1 0 7036 frm 06 0 1 2 3 4 5 6 7 8 9 cs sck si so high impedance instruction d a t a byte 7 6 5 4 3 2 1 0 10 11 12 13 14 15 7036 frm 07 w a veform inputs outputs must be steady will be steady ma y change from lo w to high will change from lo w to high ma y change from high to lo w will change from high to lo w don? care: changes allo w ed changing: state not kno wn n/a center line is high impedance symbol table
x25648/49, x25328/29, x25168/69 8 d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) 7036 frm t09 power-up timing 7036 frm t10 capacitance t a = +25 c, f = 1mhz, v cc = 5v. notes: (1) v il min. and v ih max. are f or ref erence only and are not tested. 7036 frm t11 (2) this par ameter is per iodically sampled and not 100% tested. symbol parameter limits units test conditions min. typ. max. i cc1 v cc write current (active) 5 ma sck = v cc x 0.1/v cc x 0.9 @ 2mhz, so = open i cc2 v cc read current (active) 0.4 ma sck = v cc x 0.1/v cc x 0.9 @ 2mhz, so = open i sb1 v cc standby current wdt=off 1 m a cs = v cc , v in = v ss or v cc , v cc = 5.5v i sb2 v cc standby current wdt=on 50 m a cs = v cc , v in = v ss or v cc , v cc = 5.5v i sb3 v cc standby current wdt=on 20 m a cs = v cc , v in = v ss or v cc , v cc =3.6v i li input leakage current 0.1 10 m a v in = v ss to v cc i lo output leakage current 0.1 10 m a v out = v ss to v cc v il (1) input low voltage ?.5 v cc x0.3 v v ih (1) input high voltage v cc x0.7 v cc +0.5 v v ol1 output low voltage 0.4 v v cc > 3.3v, i ol = 2.1ma v ol2 output low voltage 0.4 v 2v < v cc 3.3v, i ol = 1ma v ol3 output low voltage 0.4 v v cc 2v, i ol = 0.5ma v oh1 output high voltage v cc ?.8 v v cc > 3.3v, i oh = ?.0ma v oh2 output high voltage v cc ?.4 v 2v < v cc 3.3v, i oh = ?.4ma v oh3 output high voltage v cc ?.2 v v cc 2v, i oh = ?.25ma v olrs reset output low voltage 0.4 v i ol = 1ma symbol parameter min. max. units t pur (2) power-up to read operation 1 ms t puw (2) power-up to write operation 5 ms symbol test max. units conditions c out (2) output capacitance (so, reset , reset) 8 pf v out = 0v c in (2) input capacitance (sck, si, cs , wp ) 6 pf v in = 0v absolute maximum ratings* t emper ature under bias ........................ ?5 c to +135 c stor age t emper ature ............................. ?5 c to +150 c v oltage on an y pin with respect to v ss ....... ?.0v to +7v d .c . output current .................................................... 5ma lead t emper ature (solder ing, 10 seconds) ............ 300 c recommended operating conditions 7036 frm t07 *comment stresses abo v e those listed under ?bsolute maxim um ratings ma y cause per manent damage to the de vice . this is a stress r ating only and the functional oper ation of the de vice at these or an y other conditions abo v e those listed in the oper ational sections of this speci cation is not implied. exposure to absolute maxim um r ating conditions f or e xtended per iods ma y aff ect de vice reliability . 7036 frm t08 temp min. max. commercial 0 c 70 c industrial ?0 c +85 c supply voltage limits x25xxx ?.8 1.8v-3.6v x25xxx ?.7 2.7v to 5.5v x25xxx 4.5v-5.5v
x25648/49, x25328/29, x25168/69 9 a.c. characteristics (over recommended operating conditions, unless otherwise specified) data input timing 7036 frm t13 symbol parameter voltage range min. max. units f sck clock frequency 2.7v?.5v 1.8v?.6v 0 2 1 mhz t cyc cycle time 2.7v?.5v 1.8v?.6v 500 1000 ns t lead cs lead time 2.7v?.5v 1.8v?.6v 250 500 ns t lag cs lag time 2.7v?.5v 1.8v?.6v 250 500 ns t wh clock high time 2.7v?.5v 1.8v?.6v 200 400 ns t wl clock low time 2.7v?.5v 1.8v?.6v 200 400 ns t su data setup time 2.7v?.5v 1.8v?.6v 50 ns t h data hold time 2.7v?.5v 1.8v?.6v 50 ns t ri (3) input rise time 2.7v?.5v 1.8v?.6v 100 ns t fi (3) input fall time 2.7v?.5v 1.8v?.6v 100 ns t cs cs deselect time 2.7v?.5v 1.8v?.6v 500 ns t wc (4) write cycle time 2.7v?.5v 1.8v?.6v 10 ms equivalent a.c. load circuit at 5v v cc a.c. test conditions 7036 frm t12 5v output 100pf 5v 3.3k w reset/reset 30pf 1.64k w 1.64k w input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x0.5
x25648/49, x25328/29, x25168/69 10 data output timing 7036 frm t14 notes: (3) this par ameter is per iodically sampled and not 100% tested. (4) t wc is the time from the r ising edge of cs after a v alid wr ite sequence has been sent to the end of the self-timed inter nal non v olatile wr ite cycle . symbol parameter part number min. max. units f sck clock frequency 2.7v?.5v 1.8v?.6v 0 2 1 mhz t dis output disable time 2.7v?.5v 1.8v?.6v 250 ns t v output valid from clock low 2.7v?.5v 1.8v?.6v 200 400 ns t ho output hold time 2.7v?.5v 1.8v?.6v 0 ns t ro (3) output rise time 2.7v?.5v 1.8v?.6v 100 ns t fo (3) output fall time 2.7v?.5v 1.8v?.6v 100 ns
x25648/49, x25328/29, x25168/69 11 serial output timing serial input timing sck cs so si msb out msb? out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi high impedance
x25648/49, x25328/29, x25168/69 12 power-up and power-down timing reset output timing 7036 frm t15 notes: (5) this par ameter is per iodically sampled and not 100% tested. symbol parameter min. typ. max. units v trip reset trip point voltage, 5v device reset trip point voltage, 2.7v device reset trip point voltage, 1.8v device 4.25 2.55 1.7 4.5 2.7 1.8 v v v t purst power-up reset timeout 100 200 280 ms t rpd (5) v cc detect to reset/output 500 ns t f (5) v cc fall time 0.1 ns t r (5) v cc rise time 0.1 ns v rvalid reset valid v cc 1 v vcc t purst t purst t r t f t rpd reset (x25643) 0 v olts v trip v trip reset (x25645)
x25648/49, x25328/29, x25168/69 13 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) pin 1 pin 1 index 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 14-lead plastic small outline gull wing p a cka ge type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050" t ypical 0.050" t ypical 0.030" t ypical 14 places foo tprint 0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ?8 x 45
x25648/49, x25328/29, x25168/69 14 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ?8 x 45 8-lead plastic small outline gull wing p ackage type s note: all dimensions in inches (in p arentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
x25648/49, x25328/29, x25168/69 15 note: all dimensions in inches (in p arentheses in millimeters) 14-lead plastic, tssop , p ackage type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .01 18 (.30) 0 ?8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
x25648/49, x25328/29, x25168/69 16 ordering information part mark convention device limited w arranty de vices sold b y xicor , inc. are co v ered b y the w arr anty and patent indemni cation pro visions appear ing in its t er ms of sale only . xicor , inc. mak es no w arr anty , e xpress , statutor y , implied, or b y descr iption regarding the inf or mation set f or th herein or regarding the freedom of the descr ibed de vices from patent infr ingement. xicor , inc. mak es no w arr anty of merchantability or tness f or an y pur pose . xicor , inc. reser v es the r ight to discontin ue production and change speci cations and pr ices at an y time and without notice . xicor , inc. assumes no responsibility f or the use of an y circuitr y other than circuitr y embodied in a xicor , inc. product. no other circuits , patents , licenses are implied. u .s. p a tents xicor products are co v ered b y one or more of the f ollo wing u .s . p atents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. f oreign patents and additional patents pending. life rela ted policy in situations where semiconductor component f ailure ma y endanger lif e , system designers using this product should design the system with appropr iate error detection and correction, redundancy and bac k-up f eatures to pre v ent such an occurence . xicor s products are not author iz ed f or use in cr itical components in lif e suppor t de vices or systems . 1. lif e suppor t de vices or systems are de vices or systems which, (a) are intended f or surgical implant into the body , or (b) suppor t or sustain lif e , and whose f ailure to perf or m, when proper ly used in accordance with instr uctions f or use pro vided in the labeling, can be reasonab ly e xpected to result in a signi cant injur y to the user . 2. a cr itical component is an y component of a lif e suppor t de vice or system whose f ailure to perf or m can be reasonab ly e xpected to cause the f ailure of the lif e suppor t de vice or system, or to aff ect its saf ety or eff ectiv eness . v cc limits blank = 5v 10% 2.7 = 2.7v to 5.5v 1.8 = 1.8v to 3.6v t emperature rang e blank = commercial = 0 c to +70 c i = industr ial = ?0 c to +85 c p ac ka g e s14 = 14-lead soic s8 = 8-lead soic v14 = 14-lead tssop blank = 14-lead soic blank = 5v 10%, 0 c to +70 c i = 5v 10%, ?0 c to +85 c f = 2.7v to 5.5v , 0 c to +70 c g = 2.7v to 5.5v , ?0 c to +85 c a g = 1.8v to 3.6v , 0 c to +70 c x25648/49 p t -v x25648/49 x x x25328/29 x25168/69 blank = 8-lead soic v = 14 lead tssop blank = 5v 10%, 0 c to +70 c i = 5v 10%, ?0 c to +85 c f = 2.7v to 5.5v , 0 c to +70 c g = 2.7v to 5.5v , ?0 c to +85 c a g = 1.8v to 3.6v , 0 c to +70 c x25328/29 x x x25168/69

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